A timing analysis is an essential part of any digital
design. It is used to verify the logical operation of your circuit, and
to uncover glitches or setup/hold time violations. The timing diagram shows
how the changes from circuit inputs propagate through the circuit to the
outputs. The inputs may be asynchronous, such as switches, or synchronous
such as clocks or synchronized inputs. Feedback paths are prime candidates
for timing problems and should be examined very carefully.
Consider figure 1. This shows a simple combinational circuit of three inputs, X, Y, and Z and one output. The K map for this circuit is:
The schematic shows the circuit obtained by grouping X/Y and YZ.
Figure 2 shows the PSPICE generated timing diagram for the circuit. The diagram shows the action for a change the Y input only from zero to one. The other inputs, X and Z are held at a constant logic 1. Since the logic function is X/Y and YZ, the output should be true for Y equal to zero or one, so we should see no change in the output for this transition
A careful examination of the output, U1A:Y in the timing diagram, shows
that we do see a momentary change in the output, it "glitches"
from a logic one to logic zero momentarily.
The reason can be found by examining the timing diagram. Each gate takes
a finite time to respond to a change in input, this is the propagation
delay. Because of the extra delay in the Y signal caused by the inverter,
the AND gate U3A changes output before the AND gate U2A. This causes the
inputs to the OR gate U1A to both be zeros momentarily.
Figure 3 shows a hand-drawn timing diagram which shows the same information.
Note that the PSPICE diagram is exactly to scale so the delays can be measured
directly, the hand diagram shows the delays approximately and notations
are added to indicate the exact time.
The hand drawn diagram shows the maixmum delays, found by using the
data book maximum times. The PSPICE diagram shows min-max delays. The double
lines show that the output is uncertain between the minimum and maximum
Figures 4 and 5 show the circuit with the additional term XZ implemented.
This removes the timing hazard, and the output shows no timing glitch.
Consider the schematic shown below, the output of the
flip flop is fed back to the input through a chain of three inverters.
At every clock, the output toggles. The change in the output has to propagate
through the inverters and stabilize at the D input in time for the next
clock. At some clock frequency the circuit will fail to operate because
the output will not have had time to propagate and become stable. You can
either discover this point with analysis like a Real Engineer, or pay the
price sweating bullets in the test lab while your product malfunctions.
This timing diagram was generated using PSPICE. The propagation
delays are represented by the double yellow lines, valid logic levels are
indicated by the green lines.
Observe the delay from the positie going edge of the clock
signal to the transition of the Q output. Observe the delay through each
of the inverters. Estimate the time from when the steady state of D is
reached and the next clock edge. The clock in this circuit is 5 Mhz, estimate
when the circuit will fail to operate.